The demands for ever-increasing bandwidths in digital data communication equipment at reduced power consumption lever equipment are constantly growing. These demands not only require more efficient integrated circuit components, but also higher performance interconnect structures and devices and chip-to-substrate connections. Indeed, as one example, the International Technology Roadmap for Semiconductors (ITRS) projects that high performance chips in the very near future will have operating frequencies, both on-chip and off-chip (i.e., chip to substrate), rising above 50 GHz.
This dramatic increase in operating frequencies will require improvements over conventional integrated circuit interconnect structures and fabrication methods. As an example, current interconnect devices are not capable of enabling such high operating frequencies, thus high performance interconnect devices and structures will be needed to support high operational frequencies. In addition, cost-effective fabrication methods to produce high performance interconnect devices and structures will also be needed to provide high performance integrated circuit chips and packages. Some of the challenges in achieving high-bandwidth communication using electrical interconnects include high losses in the substrate dielectric, reflections and impedance discontinuities, and susceptibility to cross-talk.
Accordingly, there is a need for high performance interconnect device, structures, and associated fabrication methods that provide simple fabrication methods to produce interconnects having improved properties with fewer process steps and reduced costs. In addition, there is a need for improved on-chip and off-chip interconnect devices and associated fabrication methods to enable and support increased data throughput. It is to the provision of such interconnects and fabrication methods that the various embodiments of the present invention are directed.